Railroads, commuter rail and rail transit systems using solid state interlocking devices have problems which are unique to their signal engineering departments. When software mistakes are found during equipment cutovers, a signal engineer has to identify the source of the problems and correct it. Then, testing must be resumed at the very beginning of the test, not at the last point where signal system performance has been proven to be satisfactory. Many extra programing, construction and engineering man-hours can be and are consumed in the correcting-retesting these process.
Vital Sim, Inc. developed its Vital Signal Logic Simulator ("VSLS") and related products, a WINDOWS-based, group of software and graphics packages which allows signal engineers to test vital and non-vital application logic programs generated by a wide variety of development systems. VSLS is capable of accommodating Microlok I & Genisys ®, Microlok II & Genisys ®, VPI/CSEX ®, VHLC and HLC ®, Microtrax ® and Electro-Code IV and ElectrologIXS ® programmable devices.
VSLS can operate with a minimum of one monitor display on any computer that will support WINDOWS XP ® software. However, for larger locations or maximum effectiveness, operating VSLS on a two or three or even up to 8 screens for track display can be used. Screens, which are configured by the user, feature the track and signal layout and circuit nomenclature lists (tag names of input, output and internal variable names).
Unlike other simulators, VSLS permits simultaneous testing of both vital and non-vital programs for a location, as well as any slave vital units or external relays and line wire interconnections in the interlocking scheme. This feature helps to insure that individual programs execute properly as well as insuring that communication between units is correct, eliminating a major stumbling block that occurs during cutovers. Because the signal engineer can test all elements of the location simultaneously and test virtually all aspects of the programs, he can complete an integrated operational simulation of the logic more efficiently and before cutover time, debugging logic equations as he goes. Shop and in-service testing can then be concentrated on checking for wiring errors.
NOTE: VSLS is not a substitute for competent signal engineering knowledge. The user of VSLS must understand the train and signal operating sequences that require checking and the methods used to achieve the sequences. The VSLS requires the user to manually activate all inputs (e.g. switch positions, coded circuit inputs, control office commands, track circuit sequences, etc.) and he must be able to recognize when an improper or unsafe result has occurred.
Recent enhancements expand the application of VSLS beyond proving the correctness of software. The optional Lamp Out and Route Locking List Generators automatically provide cutover lists that historically have been generated by a combination of the cut-and-paste method and the mental alertness of the designer producing the lists. In the case of the Route Locking List Generator, pictorials of each route can be printed to assist with the checking and analysis. These programs provide very beneficial capabilities by substantially reducing the pre-cutover workload and assuring the validity and completeness of cutover safety checks.
Another common application of the VSLS is training. Using the Simulator’s capability to display relay logic equivalents of the logic equations provides the means to demonstrate logic formulas in graphic form. Because the display is active, it actually provides the means to show how the signal circuit works. This feature is particularly helpful in training inexperienced circuit designers or designers not familiar with programming of solid state interlocking devices. Personnel responsible for installation of the solid state interlocking devices are also able to train for the cutover by running the software in advance.
Proving out of relay-based interlocking systems, or revisions to such systems, can also be accomplished by writing equivalent logic formulas, compiling them with a vendor complier of a choice, then running them on the VSLS. Toggling to the relay-equivalent display when a false response occurs enables the signal designer to see his mistake.