Simulator Overview
Vital Sim Inc., has developed the Vital Signal Logic Simulator (VSLS), a WINDOWS® 2000/XP/7 based software and graphics package which allows signal engineers to test vital and non-vital application logic programs generated by a wide variety of development systems. At present, VSLS is capable of Microlock I & II /Genisys®, VPI/CSEX®, VHLC and ALC®, Microtrax® and Electrocode/Electrologic® programmable devices.
For maximum effectiveness, VSLS may employ multiple monitors . One screen typically features the track and signal layout. Additional screens display the circuit nomenclature list (tag names or input, output and internal variable names) and relay equivalent logic for any variable. With a simple point-and-click of the mouse, the state of any input can be toggled on or off with resulting changes in signal aspects or other outputs easily observed.
The track display currently has icons for tracks (with traffic direction), diamonds, switchs, coded tracks, slip switchs, color lights, markers, searchlights, position lights, pedestal lists, dwarf signals, cab signals, level crossings and text boxes.
Creating all the 'wire tags' for each of these drawing icons is typically done with a single click of the mouse. The simulator automatically searchs vital and non-vital programs for tags which are pertinent to the drawing element. This eliminates any typos the user may make.
After designing the track display, the simulator allows rapid testing of a location by automatically 'poping up' all tags for a drawing element , when the mouse is placed over any drawing element. The tags associated with each drawing element may be toggled or the equivalent circuits displayed with a single click of the mouse.
Unlike other simulators, VSLS permits simultaneous testing of both vital and non-vital programs for a location, as well as any slave vital units in the interlocking scheme. This feature helps to insure that individual programs execute properly as well as insuring that communication between units is correct, eliminating a major stumbling block that occurs during cutovers. Because the signal engineer can test all elements of the location simultaneously and because he can test virtually all aspects of the program, he can complete an integrated operational simulation of the logic long before cutover time, debugging logic equations as he goes. Shop and in-service testing can then be concentrated on checking for wiring errors.
Another common application of the VSLS is training. Using the Simulator's capability to display relay logic equivalents of the Boolean equations provides the means to demonstrate Boolean formulas in graphic form. Because the display is active, it actually provides the means to show how the signal circuit works. This feature is particularly helpful in training inexperienced circuit designers or designers not familiar with programming of solid state interlocking devices. Personnel responsible for installation of the solid state interlocking devices are also able to train for the cutover by running the software in advance.
Proving out of relay based interlocking systems , or revisions to such systems , can also be accomplished by writing equivalent Boolean formulas , compiling them with a vendor compiler of choice , then running them on the VSLS. Toggling to the relay equivalent display when a false response occurs enables the signal designer to see his mistake.
A Lampout Test Sheet generator is also available , which is used to produce printed reports of downgrade sequences. This is used as part of cutover documentation.
The Router and Lampout Test Sheet Generator use Microsoft Access as the data base. This allows the user to customize reports.
Simulator Operation
After using the software supplied by the vendor of the solid-state interlocking device to write and compile the device operating system program, the Interpreter Section of the Vital Signal Logic Simulator reads the text or binary files, strips out any unnecessary parts and displays the I/O bits and variables in user defined order. A user-friendly graphics utility allows the signal designer to draw the track and signal diagram, including office and/or local control panels, using basic building blocks, then assign input and output bits to the various components. The result is a simulator that allows the user to see the status of all the inputs/outputs, internal variables, timers, track circuit status and signal aspects at the same time. Nomenclatures appear adjacent to their respective icons.
Once the interface (circuit nomenclature) information has been established, the signal designer may use a mouse to select and toggle input bits. The actual logic program runs in the background and will display any changes to variable or output bits, and also updates the track and signal graphic with such information as track occupancies and changes to signal aspects, switch positions, HD Line circuits, code rates, etc. As individual bits are selected, the logic equations related to the bites are displayed at the top of the screen. If an improper response to a control function occurs, the erroneous equation is readily visible for immediate analysis and appropriate corrective action can be taken immediately by bringing up the manufacturer’s complier/editor WINDOW.
An additional feature of the basic VSLS package is the automatic, relay-equivalent conversion graphic display of the logic formulas. The display is active (permitting use of the mouse to change the status of relays shown) and interactive (between program and relay logic) permitting visual review of all circuit activity. As tests are mad, active formulas are displayed and relay-equivalents respond appropriately. Electric current flow on the appropriate path through contracts, to a particular relay coil, is indicated by a change in color of the connecting line (“wire”) and relay icon.
Yet another feature of the basic VSLS package allows the user to observe rack fault and coded circuit errors. A flashing warning indication alerts the user to the condition, allowing him to determine the cause of the fault and correct it later.